The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Data of electronic and computing devices is often written to non-volatile memory devices for storage. These memory storage devices typically include non-volatile memory media, such as flash-memory, for storing the data and a memory controller for writing the data to, or reading the data from, the non-volatile memory media. Flash-memory stores data as an electrical charge on a floating gate of a transistor configured as a flash-memory cell. Thus, to write data to a flash-memory cell, a particular level of electrical charge is applied to the floating gate that represents a value of the data. The electrical charge applied, however, may be distributed proximate, but not at this particular level, due to variances in the write process or electrical characteristics of the memory media.
A flash-memory cell is read by sensing electrical characteristics of the flash-memory cell. These electrical characteristics are affected by the level of electrical charge on the floating gate. Data bits representing the data value stored by the flash-memory cell can be determined, when a reference voltage is applied, based on whether the cell conducts. Once read, the data bits are then transferred to the memory controller for aggregation, error-correction, and subsequent transfer to a host device.
During the read process, multiple reads of the flash-memory cells may be performed to obtain an accurate measurement of a charge level stored by a flash cell due to the afore-mentioned distribution of electrical charge applied to the floating gates of the cells. Reading each cell multiple times enables various forms of error-correction, which increases reliability of the data read from the flash-memory. Multiple reads of the flash-memory cells, however, produce additional data bits that are transferred to the memory controller for error-correction. Transfer of these additional data bits increases a load, or an amount of data traffic, on a data link between the flash-memory and the memory controller. The increased load on the data link may result in reduced throughput for the data link and impaired read performance of the flash-memory device.